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ATmega128
Figure 125. General Port Pin Schematic diagram
See Boundary-Scan description
for details!
PUExn
Q
D
PUD
DDxn
Q CLR
OCxn
RESET
WDx
RDx
Pxn
Q
D
ODxn
PORTxn
Q CLR
IDxn
SLEEP
SYNCHRONIZER
RESET
WPx
RRx
RPx
D
Q
D
Q
PINxn
L
Q
Q
CLK I/O
PUD:
PUExn:
OCxn:
ODxn:
IDxn:
SLEEP:
PULLUP DISABLE
PULLUP ENABLE for pin Pxn
OUTPUT CONTROL for pin Pxn
OUTPUT DATA to pin Pxn
INPUT DATA from pin Pxn
SLEEP CONTROL
WDx:
RDx:
WPx:
RRx:
RPx:
CLK I/O :
WRITE DDRx
READ DDRx
WRITE PORTx
READ PORTx REGISTER
READ PORTx PIN
I/O CLOCK
Boundary-scan and
the Two-wire Interface
The two Two-wire Interface pins SCL and SDA have one additional control signal in the scan-
chain; Two-wire Interface Enable – T W IEN. As shown in Figure 126 , the T W IEN signal enables
a tri-state buffer with slew-rate control in parallel with the ordinary digital port pins. A general
scan cell as shown in Figure 130 is attached to the T W IEN signal.
Notes:
1. A separate scan chain for the 50 ns spike filter on the input is not provided. The ordinary scan
support for digital port pins suffice for connectivity tests. The only reason for having T W IEN in
the scan path, is to be able to disconnect the slew-rate control buffer when doing boundary-
scan.
2. Make sure the OC and T W IEN signals are not asserted simultaneously, as this will lead to
drive contention.
257
2467X–AVR–06/11
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